Job Title: Sr FPGA Engineer
Location: Boonton Township, New Jersey
Job Description :
1. Must have FPGA design principles. Working with Actel/Xilinx/Altera/Lattice FPGA.
2. Must have done RTL synthesis, constraints design, timing closure
3. Must have written test benches to verify the RTL design
4. Must have used the RTL development and debugging tools for FPGA (e.g. vivado and Synopsys)
5. Expertise in RTL debug and Validation."
Job Types: Full-time, Contract
Salary: $82,374.90 - $169,543.84 per year
Benefits:
- Dental insurance
- Health insurance
Schedule:
- 8 hour shift
Work Location: Remote
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